As known in the art, data within a computer system is typically sampled with respect to a system clock signal. For example, a data signal may be sampled at the occurrence of every rising edge of a clock signal. When the data signal is synchronized with respect to the clock signal, the clock signal is designed to produce one sample for each bit of the data signal (e.g., a rising edge of the clock signal occurs once for every bit of the data signal). Accordingly, each bit of the data signal is reliably sampled and used by the computer system to perform various functionality.
Ideally, transitions of the clock signal do not occur close to transitions of the data signal. If a data signal transitions too close to the occurrence of a clock transition, then the data may be in a transition state when the data signal is sampled, thereby causing the data to become unreliable. Furthermore, small timing variations can cause the clock transition to actually skip a bit of data and to prematurely sample the next bit of data. Therefore, great care is usually taken to keep transitions of clock signals sufficiently separated from transitions of corresponding data signals in order to ensure data reliability.
Unfortunately, sufficient separation of data signal transitions and clock signal transitions cannot always be ensured. Errors in generating data signals and clock signals as well as delays in processing data signals and clock signals cause the transitions of the two signals to fluctuate with respect to one another such that data signal transitions may occur too close to clock signal transitions to ensure reliable data. Therefore, there exists a need for a system or method of determining when data clock transitions occur with respect to clock signal transitions. This is especially true in systems that receive data signals and clock signals from external sources such as logic analyzers, for example.
Logic analyzers analyze data generated within a computer system or other digital systems in order to determine errors within the data. Therefore, logic analyzers receive data from the system under analysis and sample the data in relation to an external clock signal also received from the system. It is desirable for the logic analyzer to ensure that transitions of the received clock signal are not occurring too close to transitions of the received data signal. Otherwise, timing errors could occur, thereby corrupting the analysis of the data.
Many prior art systems test for adequate separation of data signal transitions and clock signal transitions by having the system under analysis transmit a predetermined data signal for calibration. In this regard, the sampled data is compared to the predetermined data to determine whether the two match. If the two data signals match, then it is assumed that there is adequate separation of the transitions of data and clock signals. However, if the two data signals do not match, then the timing of the two signals is adjusted and the data is then retested. This process is continued until the two signals match.
Not only does this prior art method take time to establish an accurate result, but the system under analysis must be able to generate a "known-good" signal. Furthermore, the timing of the clock signal transition with respect to the data signal transition is not actually determined, thereby making it difficult to isolate the source of error when the two data signals do not match.
Thus, a heretofore unaddressed need exists in the industry for providing a signal comparing system and method for determining transitions of a data signal relative to transitions of a clock signal so that timing errors can be detected and prevented.